1. Field of the Invention
The present invention relates to integrated circuit test apparatus, more particularly, to test systems for so-called system LSIs in which a circuit for implementing one function is formed into a macro in a single integrated circuit together with another circuit.
2. Description of the Related Art
Conventionally, circuits of, e.g., a CPU, a DSP, a DRAM, etc., are respectively mounted as independent devices on different boards. In recent years, as such circuits continue to shrink in feature size and increase in density, so-called system LSIs are increasing in which those circuits are formed as macros and integrated as verified function macros in a single integrated circuit together with other circuits. As an increasing trend, one integrated circuit includes two or more function macros.
In many cases, the layout of a function macro which assembles an independent device into a macro is fixed. It is, therefore, difficult to add a test support circuit such as a so-called logic scan circuit into a function macro later. An operation test for a system LSI including a function macro is often done by a function test of externally supplying an instruction or necessary signal, actually running the function macro, and extracting the processing result outside.
FIG. 1 is a circuit diagram showing a conventional fundamental construction for running a function test on a function macro. FIG. 1 shows only the input side of the function macro as a representative. As shown in FIG. 1, a function macro 100 comprises input terminals IN0, IN1, . . . , INnxe2x88x921, and INn. Selectors S0, S1, . . . , Snxe2x88x921, and Sn are so provided as to correspond to the respective input terminals IN0, IN1, . . . , INnxe2x88x921, and INn.
Each of the selectors S0 to Sn receives two inputs: a signal (instruction or necessary signal for a function test) input from the external input terminal of an integrated circuit including the function macro 100, in function test operation, and a signal input from a circuit of the integrated circuit other than the function macro 100 in normal operation of the integrated circuit. Each selector selects either of the signals, and supplies the selected one to the corresponding one of the input terminals IN0 to INn of the function macro 100. At this time, the selectors S0 to Sn switch the selection states of two inputs in accordance with control signals input to their control terminals.
More specifically, when the control signal represents that a test mode is set, each of the selectors S0 to Sn selects a signal input from the external input terminal of the integrated circuit in function test operation, and supplies the selected signal to the corresponding one of the input terminals IN0 to INn of the function macro 100. When the test mode is not set, i.e., a normal operation mode is set, each of the selectors S0 to Sn selects a signal input from a circuit of the integrated circuit other than the function macro 100, and supplies the selected signal to the corresponding one of the input terminals IN0 to INn of the function macro 100.
In the construction shown in FIG. 1, the terminal definition is changed by the selectors S0 to Sn to connect all the input terminals IN0 to INn of the function macro 100 to the external input terminals of the integrated circuit in test operation so as similarly to run an existing function test for an independent device on the verified function macro 100 integrated in the integrated circuit.
FIG. 2 is a circuit diagram showing a conventional construction when one integrated circuit includes two different function macros. In the construction shown in FIG. 2, one integrated circuit includes two function macros A and B (101 and 102) and another user logic 103, to which necessary signals are supplied from external input terminals 107 of the integrated circuit to run function tests sequentially. The processing results in the function macros 101 and 102 are output from external output terminals 108 of the integrated circuit to obtain the results of the function tests.
For example, function tests are sequentially run on the function macros 101 and 102, and then a function test is run on the user logic 103. In running a function test on the function macro 101, a select signal is supplied from a function macro A select terminal 104 to the function macro 101. In running a function test on the function macro 102, a select signal is supplied from a function macro B select terminal 105 to the function macro 102. In running a function test on the user logic 103, a signal representing a test mode is supplied from a control signal input terminal 106 to the user logic 103.
In running a function test on the function macro 101, signals input from the external input terminals 107 of the integrated circuit are supplied to the function macro 101. At this time, signals input from some of the external input terminals 107 are supplied to the function macro 101 via selectors 109 each for selectively outputting either of the input signal and a signal processed by the user logic 103. The processing results in the function macro 101 are output outside from the external output terminals 108 of the integrated circuit via selectors 111 each for selectively outputting any of a signal processed by the function macro 101, a signal processed by the function macro 102, and an output signal in normal operation.
In running a function test on the function macro 102, signals input from the external input terminals 107 of the integrated circuit are supplied to the function macro 102. At this time, signals input from some of the external input terminals 107 are supplied to the function macro 102 via selectors 110 each for selectively outputting either of the input signal and a signal processed by the user logic 103. The processing results in the function macro 102 are output outside from the external output terminals 108 of the integrated circuit via the selectors 111. Note that the external output terminals 108 include a dedicated terminal for outputting only a signal processed by, e.g., the function macro 102.
In running a function test on the user logic 103, signals input from the external input terminals 107 of the integrated circuit are supplied to the user logic 103. Signals processed by the user logic 103 are supplied to the function macros 101 and 102 via the selectors 109 and llzerothe processing results in the function macros 101 and 102 are output outside from the external output terminals 108 of the integrated circuit with or without the mediacy of the selectors 111.
In this construction, external terminals of the integrated circuit connected to only the function macros 101 and 102 are test terminals.
As shown in FIG. 1, an integrated circuit such as a conventional system LSI must be equipped with test terminals (external input terminals) for externally supplying various test signals to the input terminals of a function macro in order to run an existing function test even on a function macro integrated in the integrated circuit. This also applies to output terminals for outputting processing results in a function macro. For this purpose, a large number of external test terminals not used in normal operation must be provided on an integrated circuit, resulting in a highly costly integrated circuit.
As shown in FIG. 2, in an integrated circuit including function macros, the input/output terminals of function macros to be tested are selectively connected to the external test terminals of the integrated circuit to run function tests on the function macros sequentially. This prolongs the time required to test all the function macros.
As a means for preventing an increase in test time, as shown in FIG. 3, function tests are simultaneously run on two function macros 101 and 102 by simultaneously supplying a select signal for selecting function macros from a macro select terminal 112 to the function macros 101 and 102.
In this construction, however, all the input/output terminals of the function macros 101 and 102 must be connected to the external test terminals of the integrated circuit in test operation, to say the least. Thus the number of external test terminals of the integrated circuit must be increased. Such an increase in the number of test terminals greatly increases the cost.
It is an object of the present invention to suppress an increase in the number of external test terminals of an integrated circuit and reduce the cost.
It is another object of the present invention to suppress an increase in the number of external test terminals and reduce the cost in a test for an integrated circuit including function macros, and shorten the test time by simultaneously testing the function macros.
To achieve the above objects, according to the present invention, an integrated circuit test apparatus for testing a function macro integrated in an integrated circuit comprises a signal generation circuit for generating a fixed-logic signal on at least one test pattern, or a signal having a specific relationship with a signal input from a specific external input terminal of the integrated circuit, and a selection circuit for selectively supplying the signal generated by the signal generation circuit to an input terminal of the function macro.
This construction allows generating, inside the integrated circuit, a fixed-logic signal or a signal having a specific relationship with one signal input from the specific external input terminal of the integrated circuit. The integrated circuit does not require any external input terminal for inputting such signal.
For example, according to one aspect of the present invention, a fixed-logic signal generated inside the integrated circuit is selectively supplied to an input terminal of the function macro for receiving a fixed-logic signal on at least one test pattern.
This construction allows generating, inside the integrated circuit, a fixed-logic signal used to test a function macro. No fixed-logic signal need be input from the external input terminal of the integrated circuit.
According to another aspect of the present invention, an external input terminal of the integrated circuit for receiving a variable-logic signal is shared by input terminals of the function macro including terminals which do not simultaneously use one external input terminal as far as a signal input from the external input terminal is not simultaneously used by at least two input terminals of the function macro.
This construction allows appropriately supplying signals corresponding to each test pattern from one shared external input terminal to input terminals of the function macro.
According to still another aspect of the present invention, a signal input from a specific external input terminal of the integrated circuit is selectively supplied to input terminals of the function macro for receiving signals of the same logic level on at least one test pattern.
This construction allows supplying the same signal from one shared external input terminal to input terminals of the function macro.
According to still another aspect of the present invention, to an input terminal of the function macro for receiving a signal opposite in logic level to one signal on at least one test pattern, the opposite logic signal is generated from the one signal inside the integrated circuit, and selectively supplied.
This construction allows supplying one signal and an opposite logic signal from one external input terminal to input terminals of the function macro.
According to still another aspect of the present invention, to an input terminal of the function macro for receiving a signal delayed from one signal by a predetermined amount or an opposite logic signal on at least one test pattern, the signal delayed by the predetermined amount or the opposite logic signal is generated from the one signal inside the integrated circuit, and selectively supplied.
In this case, leading and trailing edge delay amounts for the one signal input from a specific external input terminal may be independently set.
This construction allows supplying one signal and a signal delayed from the one signal by a predetermined amount or an opposite logic signal from one external input terminal to input terminals of the function macro. Further, a signal whose leading and trailing edge delay amounts are different can be supplied as the signal delayed from the one signal by a predetermined amount.
According to still another aspect of the present invention, a selection state of a signal input to the input terminal of the function macro is controlled in accordance with control information set in a register in each of the above-described constructions. In this case, the control information may be set in the register via a common bus also connected to the function macro.
With this construction, the integrated circuit does not require any special external terminal for controlling the selection state of a signal input to the input terminal of the function macro.
According to the present invention, an integrated circuit test apparatus for testing a function macro integrated in an integrated circuit comprises an internal determination circuit for comparing a signal output from an output terminal of the function macro with, as an expectation signal of a test, a fixed-logic signal or a signal having a specific relationship with a signal input from a specific external input terminal of the integrated circuit to determine a test result for each signal output from at least one output terminal of the function macro, summing up determination results, and selectively supplying the summed result to a specific external output terminal of the integrated circuit.
In this construction, even if the function macro has many output terminals for outputting test results, test results output from the output terminals are determined inside the integrated circuit and output from a specific external output terminal. The integrated circuit does not require many external output terminals for outputting test results obtained from the output terminals of the function macro to outside the integrated circuit.
For example, according to one aspect of the present invention, a test result is determined for each signal output from at least one output terminal of the function macro by comparing a fixed-logic signal output from an output terminal of the function macro on at least one test pattern with a fixed-logic expectation signal generated inside the integrated circuit, and determination results are summed up and selectively supplied to a specific external output terminal of the integrated circuit.
In this construction, even if the function macro has many output terminals for outputting test results, test results output from the output terminals can be determined inside the integrated circuit and output from a specific external output terminal. Since a fixed-logic expectation signal to be compared is generated inside the integrated circuit, no fixed-logic signal need be input from the external input terminal of the integrated circuit.
According to another aspect of the present invention, an external output terminal of the integrated circuit except for the specific external output terminal is shared by output terminals of the function macro as far as signals output from the output terminals of the function macro are not simultaneously used by one external output terminal.
This construction allows appropriately supplying test result signals corresponding to each test pattern from output terminals of the function macro to one shared external output terminal.
According to still another aspect of the present invention, a test result is determined for each signal output from at least one output terminal of the function macro by comparing signals of the same logic level output from output terminals of the function macro on at least one test pattern with an expectation signal input from a specific external input terminal of the integrated circuit, and determination results are summed up and selectively supplied to a specific external output terminal of the integrated circuit.
In this construction, even if the function macro has many output terminals for outputting test results, test results output from the output terminals can be determined inside the integrated circuit and output from a specific external output terminal. An expectation signal to be compared with a signal output from at least one output terminal of the function macro is commonly input from a specific external input terminal. The integrated circuit does not require many external input terminals for inputting expectation signals of the same logic level.
According to still another aspect of the present invention, an expectation signal opposite in logic level to one expectation signal on at least one test pattern is generated from the one expectation signal inside the integrated circuit, a test result is determined for each signal output from at least one output terminal of the function macro by comparing a signal output from an output terminal of the function macro with the one expectation signal and the expectation signal opposite in logic level to the one expectation signal, and determination results are summed up and selectively supplied to a specific external output terminal of the integrated circuit.
In this construction, even if the function macro has many output terminals for outputting test results, test results output from the output terminals can be determined inside the integrated circuit and output from a specific external output terminal. An expectation signal of opposite logic is generated inside the integrated circuit from an expectation signal input from a specific external input terminal. Thus, the integrated circuit does not require many external input terminals for inputting expectation signals of opposite logic levels.
According to the still another aspect of the present invention, the one expectation signal is a signal which is identical to a reset signal or opposite in logic level to the reset signal.
In this construction, a terminal for inputting an expectation signal serves as a reset terminal.
According to still another aspect of the present invention, an expectation signal delayed from one expectation signal by a predetermined amount or an expectation signal of opposite logic on at least one test pattern is generated from the one expectation signal inside the integrated circuit, a test result is determined for each signal output from at least one output terminal of the function macro by comparing a signal output from an output terminal of the function macro with the one expectation signal and the expectation signal delayed from the one expectation signal by a predetermined amount or the expectation signal of opposite logic, and determination results are summed up and selectively supplied to a specific external output terminal of the integrated circuit.
In this case, leading and trailing edge delay amounts for the one expectation signal input from the specific external output terminal may be independently set.
In this construction, even if the function macro has many output terminals for outputting test results, test results output from the output terminals can be determined inside the integrated circuit and output from a specific external output terminal. An expectation signal delayed by a predetermined amount from an expectation signal input from a specific external input terminal, or an expectation signal of opposite logic is generated inside the integrated circuit. The integrated circuit does not require many external input terminals for inputting one expectation signal and an expectation signal delayed by a predetermined amount. As the signal delayed from the one expectation signal by a predetermined amount, a signal whose leading and trailing edge delay amounts are different can be generated inside the integrated circuit.
According to still another aspect of the present invention, determination of the test result for each signal output from the output terminal of the function macro is controlled in accordance with control information set in a register. In this case, the control information may be set in the register via a common bus also connected to the function macro.
In this construction, a special external terminal for controlling a test result in the function macro need not be formed on the integrated circuit.
As described above, according to the present invention, a signal which can be generated inside an integrated circuit is internally generated and supplied to the input terminal of the function macro on the input side of a function macro integrated in the integrated circuit. A signal which can be commonly used by input terminals is input from one external input terminal. The number of external input terminals of the integrated circuit necessary for test operation of the function macro can be reduced to reduce the cost.
A test result output from each output terminal of the function macro is determined inside the integrated circuit on the output side of the function macro integrated in the integrated circuit. A signal obtained from the determination result is output from a specific external output terminal. The number of external output terminals of the integrated circuit necessary for test operation of the function macro can be reduced to reduce the cost.
When one integrated circuit includes function macros, the input/output sides of the function macros are constituted in the above-mentioned manner and these function macros are simultaneously tested. Function macros can be tested within a short time, while the number of external terminals used in a test is suppressed small.